Dual or multi port memory is usually much lower density than single port memory because of the core cell structure. To increase the dual (multi) port memory density, pseudo dual port memory can be used. Although the external operation of pseudo dual port memory resembles the operation of true dual port memory, pseudo dual port memory incorporates a single port core cell. Pseudo dual port memory should perform multiple read and/or write operations within a single clock cycle. The timing is achieved through the use of one clock.
The dual port memory timing circuit of FIG. 4 works well at slower clock speeds, but is insufficient for higher clock soon to be achieved for input/output data transfers to a pseudo dual port memory. The clock signal is delayed for both read and write operations to allow sufficient set up and hold times for data. The rising edge of CLK generates the first ICLK for A port operation with ENA through Q1 and Q2. The falling edge of CLK generates the next ICLK for B port operation with ENB through Q3 and Q4. The read operation usually occurs by the first ICLK and the write operation usually occurs by the next ICLK. These ICLKs depends on the ENA and ENB status.
Pseudo dual port memory needs two operations—read and write operations—in one clock cycle. If the clock rising edge and falling edge are used to initiate these two operations, a first consideration is clock cycle time. Clock cycle time is set to at least twice the length of the longer cycle time in each port. The second consideration is clock duty ratio. If the clock falling edge is used for the other operation, the clock duty ratio should be included in the longer cycle time. The clock duty ratio effectively acts as a bottleneck for the higher cycle time operation.
Therefore, it would be desirable to provide a circuit and method to synchronize the write and read clock signals for a pseudo dual port memory.